Method for electrical connection between elements of a three-dimensional integrated structure and corresponding device

ABSTRACT

A link device for three-dimensional integrated structure may include a module having a first end face designed to be in front of a first element of the structure, and a second end face designed to be placed in front of a second element of the structure. The two end faces may be substantially parallel, and the module including a substrate having a face substantially perpendicular to the two end faces and carrying an electrically conducting pattern formed in a metallization level on top of the face and enclosed in an insulating region. The electrically conducting pattern may include a first end part emerging onto the first end face and a second end part emerging onto the second end face and connected to the first end part.

FIELD OF THE INVENTION

The invention relates to microelectronics, more specifically, tothree-dimensional technological platforms, and to electricalinterconnections through a silicon substrate.

BACKGROUND OF THE INVENTION

Vertical interconnection may be a challenge in three-dimensionaltechnology. Currently, these vertical electrical interconnections arefabricated in silicon through links or vias, commonly denoted by thoseskilled in the art as Through Silicon Vias (TSV). The fabrication ofthese through vias TSV may raise some problems relating notably to theirfilling (for example, with copper) when a barrier and insulation layeris implemented. In order to reach satisfactory densities of TSVs, theirform factor (height/diameter ratio) tends to be increased. Thisgenerally leads to the use of thinned semiconductor wafers, typicallywith a thickness less than 120 microns, which may pose a problem forgripping and stress during fabrication.

SUMMARY OF THE INVENTION

According to one embodiment, a three-dimensional technological form isprovided that may provide an approach to the vertical electricalinterconnection between various elements.

According to one aspect, a method is for electrical connection betweenat least one first element and one second element of a three-dimensionalintegrated structure. This method may comprise the fabrication of a linkdevice, for example, an interposer, comprising at least one modulehaving a first end face and a substantially parallel second end face.The module may comprise at least one substrate having a facesubstantially perpendicular to the two end faces. The method may alsoinclude carrying an electrically conducting pattern formed within atleast one metallization level on top of the face and enclosed within aninsulation region.

The electrically conducting pattern may comprise metal lines,advantageously formed by the same techniques as those used for theformation of the interconnection part (known by those skilled in the artunder the acronym “BEOL: Back End Of Line”) of an integrated circuit.The electrically conducting pattern may comprise at least one first endpart emerging onto the first end face and at least one second end partemerging onto the second end face, this second end part being connectedto the first end part.

In some embodiments, the method may comprise the formation of anelectrical connection between the link device and the elementscomprising at least one electrical connection between the first end partand the first element and at least one electrical connection between thesecond end part and the second element. Generally speaking, theformation of the electrical connection may comprise a relativepositioning of the link device and of the two elements so as to placethe first end face of the at least one module in front of a face of thefirst element and the second end face of the at least one module infront of a face of the second element.

According to a first embodiment, it is possible to form the at least onefirst emerging end part and the at least one second emerging end partbefore the positioning. However, in order to facilitate the later dicingstep, it may be preferable to protect the end parts during thepositioning.

It is for this reason that, according to another embodiment, theformation of the at least one first emerging end part and of the atleast one second emerging end part may comprise operations carried outbefore the positioning and operations carried out after the positioning.More precisely, according to one embodiment, the fabrication of the linkdevice may comprise the formation of an intermediate device, in whichthe at least one first end part and the at least one second end part arerespectively coated with a protection layer, positioning of theintermediate device so as to place the first end face coated with itsprotection layer in front of a face of the first element and the secondend face coated with its protection layer in front of a face of thesecond element, and after positioning of the intermediate device,exposure, for example, by etching or chemical mechanical polishing, ofthe at least one first end part and of the at least one second end partso as to make these end parts emerge onto their respective end face. Infact, irrespective of the embodiment, the typical vias TSV are replacedby an electrically conducting pattern, for example, metal lines that mayhave various shapes and dimensions.

The electrical connection between the various elements is then effectedby way of the ends of these lines. It thus becomes possible to have anextremely fine pitch between the various vertical electrical links,associated with the etching precision of the technology used, and thatcould not be obtained with typical TSVs.

An extremely high form factor for these electrical links, typicallygreater than 200, can also be achieved, with reduced problems fororifice formation and filling as was the case in the fabrication oftypical through vias. Heterogeneous materials can readily be used forthe fabrication of the electrically conducting pattern. Furthermore, itmay become easy to form vertical links incorporating, for example,various types of components such as passive components.

According to one embodiment, when the link device and the elements aredesigned to be stacked in a general stacking direction, for example, thevertical direction, the electrically conducting pattern may be formed onthe at least one substrate which sits in a plane substantiallyperpendicular to the general stacking direction, in other words thehorizontal plane. The positioning of the link device may then comprise arotation of the link device, for example, by a quarter of a turn, so asto position the first end face substantially parallel to the first faceof the first element, and to position the second end face of the modulesubstantially parallel to the second face of the second element.

In other words, the pattern or patterns are formed in a typical manneron a substrate placed horizontally. The idea is that, during the stepfor assembly/placement, the modules thus formed are subjected to a stepfor rotation by 90°. Consequently, the horizontal metal lines may becomede facto vertical electrical links. This step can be developed andincluded in the functionalities provided by an industrial tool known asa “flip chip bonding” tool. As previously indicated, the electricallyconducting pattern can comprise elements of any given shape. However,generally, the electrically conducting pattern notably may comprisemetal lines.

Thus, according to one embodiment, the formation of the electricallyconducting pattern may comprise the formation, within the at least onemetallization level, of a set of metal lines, at least some of whichemerge onto the first end face in order to form at least one portion ofthe first end part, and onto the second end face in order to form atleast one portion of the second end part. However, the formation of theelectrically conducting pattern can also comprise the formation, on theface of the substrate, of several substantially parallel metallizationlevels mutually separated by insulating regions. Each metallizationlevel may comprise a set of metal lines at least some of which emergeonto the first end face in order to form at least one portion of thefirst end part and onto the second end face in order to form at leastone portion of the second end part. The metal lines formed on ametallization level may be totally insulated from the metal lines formedon another metallization level.

In other embodiments, it is possible for at least some of the lines ofone metallization level to be connected to certain lines of othermetallization levels depending on the topography of the desired finalvertical electrical link. Thus, according to one embodiment, theformation of the electrically conducting pattern may comprise theformation of at least one electrically conducting interconnection hole(or via) between a metal line of one of the metallization levels and ametal line of another metallization level. These lines and these viascan be formed in a typical manner, for example, by a method of thedouble-Damascene type, as will be appreciated by those skilled in theart.

Although a metal line can run between the first end part of the moduleand the second end part of the module, it is also possible for some ofthe metal lines to be designed to connect two different locations of thesame end part. Thus, according to one embodiment, the formation of theelectrically conducting pattern may comprise the formation, within atleast one metallization level, of a set of metal lines at least one ofwhich emerges at two different locations on one of the two end faces, soas to respectively form at least one portion of the first or of thesecond end part.

So as to obtain a thicker module, it is also possible for thefabrication of the at least one module to comprise the fabrication ofseveral elementary blocks, each comprising a substrate carrying anelectrically conducting pattern formed in at least one metallizationlevel, and a stacking of these elementary blocks. The formation of theelectrical connection between the link device and the elements maycomprise at least one electrical connection between the first end partof each pattern and the first element, and at least one electricalconnection between the second end part of each pattern and the secondelement.

Thus, for example, each elementary block may comprise a substrate,preferably thinned, carrying one or more metallization levels, then thevarious elementary blocks are assembled, for example, by bonding, so asto form the module. The vertical electrical connection density can thusbe increased. In practice, according to one embodiment, the fabricationof the modules may comprise the fabrication of an assembly comprisingthe modules as a block and the dividing up of the assembly between themodules, for example, by sawing, so as to obtain the modules. It is alsopossible to produce a link device comprising several assembled modules.

Thus, according to one embodiment, the fabrication of the link devicemay comprise the fabrication of several modules and the assembly of themodules in such a manner that the respective first end faces of themodules are in the same plane and form a first end face of the device,and in such a manner that the respective second end faces of the modulesare in a second plane and form a second end face of the device. Theassembly of the modules can comprise a step for rotation of theaforementioned modules, so as notably to transform the horizontal linesinto vertical links. The link device may then be positioned so as toplace its first end face in front of the face of the first element, andits second end face in front of a face of the second element. The methodmay comprise the formation of an electrical connection between the linkdevice and the elements, this electrical connection comprising at leastone electrical connection between the first end part of each pattern andthe first element, and at least one electrical connection between thesecond end part of each pattern and the second element.

Another aspect is directed to a link device for a three-dimensionalintegrated structure. The link device may comprise at least one modulehaving a first end face designed to be in front of a first element ofthe structure, and a second end face designed to be placed in front of asecond element of the structure. The two end faces may be substantiallyparallel, and the module may comprise at least one substrate having aface substantially perpendicular to the two end faces and carrying anelectrically conducting pattern formed in at least one metallizationlevel on top of the face and enclosed in an insulating region. Theelectrically conducting pattern may comprise at least one first end partemerging onto the first end face and at least one second end partemerging onto the second end face and connected to the first end part.

According to one embodiment, the electrically conducting pattern maycomprise, within the at least one metallization level, a set of metallines, at least some of which comprising first ends emerging onto thefirst end face and second ends emerging onto the second end face. The atleast one first end part of the pattern may comprise the first emergingends and the at least one second end part of the pattern comprising thesecond emerging ends.

According to one embodiment, the electrically conducting pattern maycomprise, on the face of the substrate, several substantially parallelmetallization levels mutually separated by insulating regions. Eachmetallization level may comprise a set of metal lines, at least some ofwhich comprising first ends emerging onto the first end face and secondends emerging onto the second end face. The at least one first end partof the pattern may comprise the first emerging ends of each set oflines, and the at least one second end part of the pattern may comprisethe second emerging ends of each set of lines.

According to one embodiment, the electrically conducting pattern maycomprise at least one electrically conducting interconnection holebetween a metal line of one of the metallization levels and a metal lineof another metallization level. According to another embodiment, theelectrically conducting pattern may comprise, within at least onemetallization level, a set of metal lines, at least one of whichemerging at two different locations on one of the two end faces. The atleast one first end part or the at least one second end part of thepattern may comprise the two ends of the at least one line emerging atthe two different locations.

Additionally, the at least one module may comprise several stackedelementary blocks, each elementary block comprising a substrate carryingan electrically conducting pattern formed in at least one metallizationlevel. The device may comprise several modules assembled in such amanner that the respective first end faces of the modules are in thesame plane and form a first end face of the device, and in such a mannerthat the respective second end faces of the modules are in the sameplane and form a second end face of the device. The first end face ofthe device may be designed to be in front of the face of the firstelement and the second end face of the device being designed to be infront of a face of the second element.

Another aspect is directed to a three-dimensional integrated structurecomprising a link device such as defined hereinabove. At least one firstelement may be electrically coupled to the at least one first end partof at least one electrically conducting pattern, and at least one secondelement may be electrically coupled to the at least one second end partof at least one electrically conducting pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and features of the invention will become apparent uponexamining the detailed description of non-limiting embodiments and theirimplementation, and the appended drawings in which:

FIGS. 1 to 5 illustrate an embodiment of a method, according to thepresent invention.

FIG. 6 illustrates another embodiment of a module of a link device,according to the present invention.

FIG. 7 illustrates an embodiment of a three-dimensional integratedstructure, according to the present invention. incorporating an exampleembodiment of a link device, according to the present invention.

FIGS. 8 to 10 illustrate other embodiments, according to the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In FIG. 1, the references PQ1 and PQ2 denote semiconductor wafers knownto those skilled in the art, for example, discs of 200 or 300 mmdiameter. On various portions PRT of the substrate SB (for example, madeof silicon) of each wafer, an electrically conducting pattern MTF isformed on top of the plane upper face of the substrate here comprisingelectrically conducting lines, for example, parallel metal lines made ofcopper LG. These lines are formed within a metallization level in ananalogous fashion to that used to form the interconnection part, or“BEOL”, of an integrated circuit. A typical single- or double-Damascenemethod may for example be used.

The geometry of the pattern MTF is chosen here according to the finalgeometry of the desired vertical electrical link between variouselements of a three-dimensional integrated structure. The minimum pitchfor spacing between the lines LG is defined here by the etchingprecision of the technology used.

It goes without saying that, depending on the desired final topographyfor the vertical electrical link, several metallization levels may beformed on top of each portion PRT. The pattern MTF can then comprise,within each metallization level, a set of lines LG. Also, although thelines have been shown here as rectilinear and parallel, they may be ofany given shape depending on the desired final geometry for the verticallink. Furthermore, at least some of the lines in different metallizationlevels can be connected together by conventional interconnection vias orholes. These lines and these vias can then be formed, for example, by atypical double-Damascene method.

Then, as illustrated in FIG. 2, the various wafers PQi are preferablythinned (step 20) then assembled to one another, for example, by bonding21, so as to obtain an assembly of thinned wafers PQAi, each carryingelectrically conducting patterns. The various wafers PQi can be thinned,for example, to a thickness of 300 microns. The assembly ENS thusobtained is illustrated in more detail in FIG. 3.

This assembly ENS comprises, in its lower part, the thinned wafer PQA1comprising the thinned substrate SB1 carrying, on its plane upper faceFS1, an insulating region RIS1 enclosing an electrically conductingpattern MTF1. This pattern MTF1 comprises metal lines formed withinvarious metallization levels Mk, Mk+1. Some of these lines arefurthermore mutually connected by vias V.

The thinned wafer PQA2 is situated on top of the insulating region RIS1comprising the thinned substrate SB2 carrying, on its upper face FS2, aninsulating region RIS2 enclosing another pattern MTF2 here alsocomprising metal lines formed within various metallization levels Mj,Mj+1. Here again, some of the metal lines in two adjacent metallizationlevels are mutually connected by vias V.

Lastly, the region RIS2 carries the thinned substrate SB3 of the waferPQA3. The upper face FS3 of the substrate SB3 carries an insulatingregion RIS3 enclosing a third pattern MT3 also comprising metal linesformed within various metallization levels Mi, Mi+1. This assembly ENSin fact comprises various modules which will subsequently, asillustrated in FIG. 4, undergo a dicing operation 40, for example, asawing operation, between the various modules of the assembly ENS so asto divide up these modules and to obtain individual modules MD.

The module MD in FIG. 4, separated after the dicing process 40,therefore here comprises three elementary blocks BE1, BE2, BE3. Eachelementary block BEi comprises a substrate SBi carrying on its upperface FSi an insulating region RISi incorporating an electricallyconducting pattern MTFi.

As can furthermore be seen in FIG. 4, the metal lines of the variouselectrically conducting patterns emerge onto a face of the module hereforming a first end face FAX1, this face FAX1 being perpendicular to theupper faces FSi of the substrates SBi. It should be noted that at leastone of the substrates can be a high-resistivity silicon substrate (HR).At least one of the substrates can be an active silicon substrate, inother words incorporating active components, such as transistors. Atleast one of the substrates can comprise a material having a differentcoefficient of thermal expansion (CTE) (example: porous silicon) inorder to allow a better mechanical resistance to temperature. At leastone of the substrates can be formed by a ferromagnetic composite (e.g.YiG) in order to allow the fabrication of inductive elements.

As illustrated in FIG. 5, the individual module MD also comprises asecond end face FAX2 parallel to the first end face FAX1 and onto whichalso emerge at least some of the metal lines of the various electricallyconducting patterns. Whereas the various metallization levels of thevarious electrically conducting patterns of the various modules areformed on the plane and horizontal upper faces of the substrates, andthe various substrates are subsequently stacked in a vertical stackingdirection DR, the modules MD then undergo a rotation of a quarter of aturn, in such a manner, as illustrated on the right-hand part of FIG. 5,that the two end faces FAX1 and FAX2 of the modules MD becomehorizontal, in other words perpendicular, to the direction of verticalstacking. The lines of the various patterns that are initiallyhorizontal then become vertical lines and hence are ready to formvertical electrical links allowing, for example, two elements to beinterconnected that will come respectively into contact on the emergingportions of the metal lines respectively situated on the faces FAX1 andFAX2, as will be explained in more detail hereinafter.

FIG. 6 illustrates the structure of a module MD in greater detail. Thelatter is shown after rotation by a quarter of a turn. On this moduleMD, the three elementary blocks BE1, BE2, BE3 can be seen, eachcomprising a substrate SBi carrying on their face FSi an insulatingregion RISi containing an electrically conducting pattern MTFi. Themodule MD comprises a first end face FAX1 perpendicular to the faces FSiof the substrates SBi, together with a second end face FAX2 parallel tothe end face FAX1. Each electrically conducting pattern MTFi includes afirst end part emerging onto the first end face FAX1 and a second endpart emerging onto the second end face FAX2.

More precisely, the pattern MTF1 includes a first end part PX11comprising the emerging ends of the various metal lines, whereas thesecond pattern MTF2 also comprises a first end part PX21 and the patternMTF3 comprises a first end part PX31. The second end part of the patternMTF3 is referenced PX32 and emerges onto the second end face FAX2.

As illustrated in FIG. 6, the patterns MTFi comprise metal lines, forexample, the lines LG30 and LG31 of the pattern MTF3, running betweenthe two end faces FAX1 and FAX2. These lines allow a first element inelectrical contact with the first end portions PX11, PX21 and PX31 ofthe various patterns to be vertically interconnected with a secondelement in electrical contact with the second end parts of the variouspatterns. This is illustrated more particularly in FIG. 7.

Before describing this figure, it should be noted that the length L1 ofthe module is fixed notably by the number of stacked thinned wafers.Typically, the length L1 is of the order of 0.5 to 2 mm. In contrast,the length L2 is not limited.

Furthermore, whereas the spacing pitch between the various modules isconstant in the direction L1, and notably depends on the thickness ofthe thinned substrates, the spacing pitch between the various lines ofthe various patterns, in other words the pitch in the direction L2, isnot constant.

If reference is now made more particularly to FIG. 7, which illustratesschematically one example of a three-dimensional integrated structureSTR, it can be seen that the link device DIS comprises an assembly ofseveral modules MD1, MD2, MD3. These various components can, forexample, be mutually bonded as a block by a molding resin or else anyother material 30 allowing such an assembly to be formed. This materialcan, for example, be a material with a lower coefficient of thermalexpansion than that of silicon.

The first end faces FAX1 of the various modules are situated in the sameplane so as to form a first end face FAXD1 for the device DIS.Similarly, the second end faces FAX2 of the various modules are situatedin the same plane so as to form a second end face FAXD2 for the deviceDIS.

The assembly of the various modules can be carried out in an automatedfashion by way of a machine programmed to place the various modules withrespect to one another according to the desired final geometry of thefinal electrical interconnection. During this placement, the modulesundergo the aforementioned rotation of a quarter of a turn.

The device DIS here forms a passive interposer allowing the threeelements EL1, EL2 and EL3 to be electrically connected. More precisely,the elements EL1 and EL2 are, for example, integrated circuits,electrically connected on the first end face FAXD1 of the device DIS byway, for example, of connection beads or “bumps”. Here the secondelement EL2 is an integrated circuit board (PCB: Printed Circuit Board)electrically connected to the second end face FAXD2 of the device DISalso by way of bumps BL.

The various bumps come into electrical contact, for example, bysoldering, with the end parts of the various patterns, in other wordsthe emerging ends of the various metal lines of the patterns. Thevertical electrical link between the element EL2 and the elements EL1and EL3 is thus ensured.

Furthermore, it is also possible to create two-dimensional verticalelectrical links by forming, for example, a metal line LG20 with astaircase (or diagonal) shape allowing two elements (here the elementsEL2 and EL3) to be vertically connected between two points not situatedon the same vertical line. This advantageously allows the number ofmetal levels needed for the routing or for the redistribution to belimited.

Similarly, it is also possible, as illustrated by the line LG21, for twoelements EL1 and EL3 disposed on the same end face FAXD1 of the deviceDIS to be electrically connected. For this purpose, the line LG21emerges at two different locations EN1, EN2 on the face FAX1 of thecorresponding module, here the module MD2.

It can therefore be seen that it is possible, according to one aspect,to very easily create routing levels with various shapes within thedevice DIS. Vertical electrical links are also obtained that can exhibitvery high form factors with very tight spacing pitches. The finalgeometry of the vertical and/or horizontal electrical link between thevarious elements of the structure STR is obtained by the variousgeometries of the plane patterns MTF formed on the various substrates.At certain locations, high densities of vertical links and, in otherlocations, lower densities can thus be obtained.

Furthermore, electrically conducting patterns of all shapes can readilybe formed, for example, inductive spirals or else capacitor electrodes.The present embodiments are not limited to the embodiments andimplementations which have just been described but also cover all theirvariants.

Thus, as illustrated in FIG. 8, it is possible to form, on top of atleast one of the end faces, at least one redistribution metal line orlayer (known by the acronym RDL: ReDistribution Layer), running parallelto this end face and contacting at least one of the end parts. Thisallows the possibility of connecting a connection bump between two endparts and thus reducing the connection pitch and/or of providing agreater flexibility in the location of the bumps.

In the example illustrated, a redistribution line 10A contacts a singleend part PX31 and another 10B contacts two end parts of two adjacentpatterns MTF1, MTF2. Of course, several levels of redistribution can beprovided.

Furthermore, in the embodiments that have just been described, theemerging nature of the end parts has been created prior to the rotationof the device. However, in order to protect these end parts, coatingthese end parts with a protection layer CP prior to rotation may beincluded as illustrated in FIG. 9. This protection layer can be a partof the insulating region obtained during the dicing. Then, afterrotation (FIG. 10), this protection layer CP is removed, for example, bychemical etching or chemical mechanical polishing, so as to expose theend parts.

1-25. (canceled)
 26. A method for electrical connection between at leastone first element and at least one second element of a three-dimensionalintegrated structure, the method comprising: making a link device havingat least one module having a first end face, and a substantiallyparallel second end face; the at least one module comprising at leastone substrate having a face substantially perpendicular to the first andsecond end faces, an electrically conductive pattern formed within atleast one metallization level on top of the face, and an insulatingregion enclosing the at least one metallization level; forming theelectrically conductive pattern to comprise at least one first end partemerging onto the first end face, and at least one second end partemerging onto the second end face and connected to the at least onefirst end part; and forming an electrical connection between the linkdevice and the at least one first and second elements, the electricalconnection comprising a connection between the at least one first endpart and the at least one first element, and a connection between the atleast one second end part and the at least one second element.
 27. Themethod according to claim 26 wherein forming the electrical connectioncomprises positioning the link device and the at least one first andsecond elements so as to place the first end face of the at least onemodule in front of a face of the at least one first element and thesecond end face of the at least one module in front of a face of the atleast one second element.
 28. The method according to claim 27 furthercomprising forming the at least one first end part and the at least onesecond end part before the positioning.
 29. The method according toclaim 27 wherein forming the at least one first end part and the atleast one second end part is performed before and after positioning. 30.The method according to claim 29 wherein making the link devicecomprises: forming an intermediate device in which the at least onefirst end part and the at least one second end part are respectivelycoated with a protection layer; positioning of the intermediate deviceso as to place the first end face coated with a respective protectionlayer in front of the face of the at least one first element and thesecond end face coated with a respective protection layer in front ofthe face of the at least one second element; and after positioning ofthe intermediate device, exposing the at least one first end part andthe at least one second end part so as to make these parts emerge ontorespective first and second end faces.
 31. The method according to claim27 wherein the link device and the at least one first and secondelements are designed to be stacked according to a general stackingdirection; further comprising forming the electrically conductivepattern on the at least one substrate in a plane substantiallyperpendicular to the general stacking direction; and wherein positioningcomprises rotating at least one of the link device and the intermediatedevice so as to position the first end face substantially parallel tothe face of the at least one first element and to position the secondend face substantially parallel to the face of the at least one secondelement.
 32. The method according to claim 26 wherein forming theelectrically conductive pattern comprises forming a set of electricallyconductive lines, at least some of the set of electrically conductivelines emerging onto the first end face to form a portion of the at leastone first end part and onto the second end face to form a portion of theat least one second end part.
 33. The method according to claim 32wherein forming the electrically conductive pattern comprises forming onthe face of the at least one substrate a plurality of substantiallyparallel metallization levels mutually separated by a plurality ofinsulating regions, each metallization level comprising a set ofelectrically conductive lines, at least some of the set of electricallyconductive lines emerging onto the first end face to form a portion ofthe at least one first end part and onto the second end face to form aportion of the at least one second end part.
 34. The method according toclaim 33 wherein forming of the electrically conductive patterncomprises forming at least one electrically conductive via electricalinterconnection between an electrically conductive line of one of theplurality of metallization levels and an electrically conductive line ofanother one of the plurality of metallization levels.
 35. The methodaccording to claim 26 wherein forming the electrically conductivepattern comprises forming, within the at least one metallization level,a set of electrically conductive lines, at least one of the set ofelectrically conductive lines emerging at two different locations on oneof the first and second end faces so as to respectively form at least aportion of the at least one first and second end parts.
 36. The methodaccording to claim 26 wherein making of the at least one modulecomprises: making a plurality of elementary blocks, each elementaryblock corresponding to the at least one module; and stacking theplurality of elementary blocks.
 37. The method according to claim 36wherein making the link device comprises forming at least oneredistribution electrically conductive level contacting at least one ofthe at least one first and second end parts and running parallel to thecorresponding first and second end face.
 38. The method according toclaim 26 wherein making the link device comprises: making a plurality ofmodules; and assembling of the plurality of modules so that therespective first end faces of the plurality of modules are in a sameplane and form the first end face of the link device, and so that therespective second end faces of the plurality of modules are in the sameplane and form the second end face of the link device; wherein the linkdevice is positioned to place the first end face in front of a face ofthe at least one first element and the second end face in front of aface of the at least one second element.
 39. The method according toclaim 38 wherein making of the plurality of modules comprises making anassembly comprising the plurality of modules as a block, and dicing upof the assembly between the plurality of modules so as to obtain theplurality of modules.
 40. A method for making a link device between afirst element and a second element, the method comprising: forming thelink device to have a first end face adjacent the first element, and asubstantially parallel second end face adjacent the second element, thelink device comprising at least one substrate having a facesubstantially perpendicular to the first and second end faces, anelectrically conductive pattern on the face, and an insulating regionenclosing the electrically conductive pattern; forming the electricallyconductive pattern to comprise at least one first end part emerging ontothe first end face, and at least one second end part emerging onto thesecond end face and connected to the at least one first end part; andforming an electrical connection between the link device and the firstand second elements.
 41. The method according to claim 40 whereinforming the electrical connection comprises positioning the link deviceand the first and second elements so as to place the first end face infront of a face of the first element and the second end face in front ofa face of the second element.
 42. The method according to claim 41further comprising forming the at least one first end part and the atleast one second end part before the positioning.
 43. The methodaccording to claim 41 wherein making the link device comprises: formingan intermediate device in which the at least one first end part and theat least one second end part are respectively coated with a protectionlayer; positioning the intermediate device so as to place the first endface coated with a respective protection layer in front of the face ofthe first element and the second end face coated with a respectiveprotection layer in front of the face of the second element; and afterpositioning of the intermediate device, exposing the at least one firstend part and the at least one second end part so as to make these partsemerge onto respective first and second end faces.
 44. A link device forthree-dimensional integrated structure comprising: at least one modulehaving a first end face configured to be in front of a first element,and a second end face configured to be placed in front of a secondelement, the first and second end faces being substantially parallel;said at least one module comprising at least one substrate having a facesubstantially perpendicular to said first and second end faces, at leastone metallization level on top of the face and defining an electricallyconductive pattern, and an insulating region enclosing said at least onemetallization level; said electrically conductive pattern comprising atleast one first end part emerging onto the first end face, and at leastone second end part emerging onto the second end face and connected tothe first end part.
 45. The link device according to claim 44 whereinsaid electrically conductive pattern comprises a set of electricallyconductive lines.
 46. The link device according to claim 45 wherein saidelectrically conductive pattern comprises, on the face of said at leastone substrate, a plurality of substantially parallel metallizationlevels; and wherein said at least one module comprises a plurality ofinsulating regions mutually separating said plurality of substantiallyparallel metallization levels.
 47. The link device according to claim 46wherein each metallization level comprises a set of electricallyconductive lines, at least some of said set of electrically conductivelines comprising first ends emerging onto said first end face and secondends emerging onto said second end face.
 48. The link device accordingto claim 47 wherein said electrically conductive pattern comprises atleast one electrically conducting interconnection via between anelectrically conductive line of one of the metallization levels and anelectrically conductive line of another metallization level.
 49. Thelink device according to claim 44 wherein said electrically conductivepattern comprises a set of electrically conductive lines, at least oneof said set of electrically conductive lines emerging at two differentlocations on one of said first and second end faces, one of said atleast one first end part and said at least one second end part of saidelectrically conductive pattern comprising two ends of the at least oneline emerging at the two different locations.
 50. The link deviceaccording to claim 44 wherein said at least one module comprises aplurality of stacked elementary blocks, each elementary block comprisinga substrate, and an respective electrically conductive pattern formed.51. The link device according to claim 50 wherein at least one of saidsubstrates from said plurality of stacked elementary blocks comprises atleast one of a ferromagnetic composite, a material having a coefficientof thermal expansion different from at least one other substrate, and anactive substrate.
 52. The link device according to claim 44 furthercomprising at least one redistribution electrically conductive levelcontacting at least one of the at least one first and second end partsand running parallel to a corresponding end face.
 53. The link deviceaccording to claim 44 further comprising a plurality of modulesassembled so that the respective first end faces of said plurality ofmodules are in a same plane and form said first end face, and so thatthe respective second end faces of said plurality of modules are in thesame plane and form said second end face, said first end face configuredto be in front of the face of said first element and said second endface configured to be in front of a face of said second element.
 54. Thelink device according to claim 53 further comprising, for the assemblyof said plurality of modules, a material with a lower coefficient ofthermal expansion than that of silicon.
 55. An electronic devicecomprising: first and second elements; and a link device connecting saidfirst and second elements and having a first end face configured to beadjacent said first element, and a second end face configured to beadjacent said second element, the first and second end faces beingsubstantially parallel; said link device comprising at least onesubstrate having a face substantially perpendicular to said first andsecond end faces, an electrically conductive pattern on the face, and aninsulating region enclosing said electrically conductive pattern; saidelectrically conductive pattern comprising at least one first end partemerging onto the first end face, and at least one second end partemerging onto the second end face and connected to the first end part.56. The electronic device according to claim 55 wherein saidelectrically conductive pattern comprises a set of electricallyconductive lines.
 57. The electronic device according to claim 55wherein said electrically conductive pattern comprises, on the face ofsaid at least one substrate, a plurality of substantially parallelmetallization levels; and wherein said link device comprises a pluralityof insulating regions mutually separating said plurality ofsubstantially parallel metallization levels.